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?1 CXD2312R e94z29d0z-ps 9-bit 20msps video a/d converter description the CXD2312R is a 9-bit cmos a/d converter for video applications. this ic is ideally suited for the a/d conversion of video signals in tvs, vcrs, camcorders, etc. features resolution: 9-bit 0.5 lsb (d.l.e.) maximum sampling frequency: 20msps low power consumption: 130mw (at 20msps typ.) (not including reference current) ttl compatible input tri-state ttl compatible output (dv dd = 3.3v) low input capacitance reference impedance: 300 ? (typ.) absolute maximum ratings (ta = 25?) supply voltage v dd 7v reference voltage vrt, vrb v dd + 0.5 to v ss ?0.5 v input voltage (analog) v in v dd + 0.5 to v ss ?0.5 v input voltage (digital) v ih , v il v dd + 0.5 to v ss ?0.5 v output voltage (digital) v oh , v ol v dd + 0.5 to v ss ?0.5 v storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 5.0 0.25 v dv dd , dv ss 3.0 to 5.25 v | dv ss ?av ss | 0 to 100 mv reference input voltage vrb more than 1.8 v vrt to av dd ?0.4 v analog input v in more than 1.8vp-p clock pulse width t pw 1 25 (min.) ns t pw 0 25 (min.) ns operating ambient temperature topr ?0 to + 75 ? structure silicon gate cmos ic sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin lqfp (plastic)
?2 CXD2312R block diagram aa aa aa aaa a a a a a a a a a a a a a a a aaa aaaa a aa a aaaa aaa a a a a a a a a a a a a a a a aaa aaa a a a a a a aaa aaa a a a a a a a a a aaa aaaa aaaa + + 8 dac coarse comparate & encode calibration unit fine comparate & encode fine latch coarse correction & latch timing gen d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) minv linv testmode cal sel reset v in vrt vrt vrb vrb clk ce oe 2 3 4 5 8 9 10 11 12 15 17 18 19 20 21 22 23 24 26 27 28 29 30 39 36 35 34 41 aaaaaa a aaaa a aaaaaa aa aa aa aa sense amp sense amp av ss av dd auto calibration pulse generator pin configuration ce oe clk minv linv testmode av dd sel dv ss reset tin to tstr at v in nc cal ts av ss av ss dv dd nc nc dv ss av ss vrb vrb nc nc nc vrt vrt av ss av ss av dd av dd d1 d2 d3 d4 dv ss dv dd d5 d6 d7 d8 d0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 nc
3 CXD2312R pin description dv dd dv ss pin no symbol equivalent circuit description 2 to 5 8 to 12 d0 to d8 13 7, 45 6, 16, 48 27, 28, 36, 43, 44 to dv dd dv ss av ss 17 sel 22 clk cal 41 15 reset d0 (lsb) to d8 (msb) output. test pin. ts = high: high impedance state digital v dd . digital v ss . analog v ss . calibration input pulse select after completion of the startup calibration. high : internal pulse generation low : external input clock pin. calibration pulse input. calibration circuit reset and startup calibration restart. av dd av ss 17 av dd av ss 22 av dd av ss 41 av dd av ss 15
4 CXD2312R av dd av ss 29 30 34 35 pin no. symbol equivalent circuit description 14 tin 34, 35 vrb 23 oe ce 24 test signal input. normally fixed to av dd or av ss . reference top. reference bottom. test signal output. ts = high: high impedance state d0 to d8 output enable. low : output state high : high impedance state chip enable. low : active state high : standby state 29, 30 vrt 38 at 42 ts 37 tstr test signal input. normally fixed to av dd . test signal input. normally fixed to av ss . av dd av ss 23 av dd av ss 24
5 CXD2312R pin no. symbol equivalent circuit description 20 linv 39 v in test mode. high : output state low : output fixed output inversion. high : d0 to d7 are inverted and output. output inversion. high : d8 is inverted and output. analog input. 19 testmode 21 minv 18, 25, 26 av dd av dd av ss 39 analog v dd . av dd av ss 19 av dd av ss 20 av dd av ss 21
6 CXD2312R input signal voltage digital output code msb lsb step vrt vrb 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 255 256 511 testmode linv minv d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 p n p n 0 1 0 1 p n p n 1 0 1 0 p n p n 0 1 0 1 p n p n 1 0 1 0 p n p n 0 1 0 1 p n p n 1 0 1 0 p n p n 0 1 0 1 p n p n 1 0 1 0 p p n n 0 0 1 1 digital output the following table shows the correlation between the analog input voltage and the digital output code (testmode = 1, linv, minv = 0) the following table shows the output state for the combination of testmode, linv, and minv states. p: forward-phase output n: inverted output timing chart 1 t dl t pw 1t pw 0 clock analog input data output n 3n 2n n 1 1.65v 1.65v (dv dd = 3.3v) 2.5v (dv dd = 5.0v) hold n hold n + 1 hold n + 2 hold n + 3 t sl t sh timing chart 2 high impedance t pez t pze active active 1.65v 1.65v output enable (oe) data output 1.65v (dv dd = 3.3v) 2.5v (dv dd = 5.0v)
7 CXD2312R electrical characteristics (fc = 20msps, av dd = 5v, dv dd = 3.3v, vrb = 2.0v, vrt = 4.0v, ta = 25 c) fc max fc min ia dd id dd ia st id st i rt i rb bw c in r ref e ot e ob v cal 1 v cal 2 v ih v il a ih a il i ih i il i oh i ol i ozh i ozl t pez t pze e l e d dg dp t dl t sh t sl max. conversion rate min. conversion rate analog digital analog digital analog input band analog input capacitance reference resistance value (vrt vrb) tri-state output disable time tri-state output enable time integral non-linearity error differential non-linearity error differential gain error differential phase error output data delay sampling delay 20 21 1.6 5.0 3.0 210 30 30 2.3 10 4.0 3.5 20 10 8 0 24 1.7 7.5 5.5 35 10 300 8.0 12 2.5 1.0 25 15 0.5 0.3 1.0 0.3 13 6 2 0.5 28 1.8 1.0 1.0 10.0 8.0 390 30 30 0.8 20 5 5 1 1 30 20 1.0 0.5 18 4 item symbol conditions min. typ. max. unit supply current msps ma a ma mhz pf ? mv v v a a a ns ns % deg ns ns lsb ma standby current reference pin current offset voltage analog input current startup calibration start voltage digital input voltage digital input current digital output current digital output current f in = 1.0khz triangular wave input f in = 1.0khz triangular wave input ce = high e ot = theoretical value-actual measured value eob = actual measured value- theoretical value 1db v oh = dv dd 0.5v v oh = 0.4v v oh = dv dd v ol = 0v dv dd = max oe = av ss dv dd = min clock not synchronized for active high impedance clock not synchronized for high impedance active ntsc 40 ire mod ramp, fc = 14.3msps av dd = 4.75v to 5.25v c l = 20pf v il = 0v v ih = dv dd v in = 4v v in = 2v oe = av dd dv dd = max av dd av ss vrt vrb
8 CXD2312R application circuit 1. startup calibration + internal auto calibration digital output 2.0v av ss 4.0v 2.0v av dd av ss dv dd dv ss 4.0v av dd av ss av dd av ss dv ss clock input ce oe clk minv linv testmode av dd sel dv ss reset tin to tstr at v in nc cal ts av ss av ss dv dd nc nc dv ss av ss vrb vrb nc nc nc vrt vrt av ss av ss av dd av dd d1 d2 d3 d4 dv ss dv dd d5 d6 d7 d8 d0 is all 0.1f sample & hold 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av dd nc snr sfdr snr sfdr 53 53 53 51 51 49 68 66 66 62 56 51 item symbol conditions min. typ. max. unit db db f in = 100khz f in = 500khz f in = 1mhz f in = 3mhz f in = 7mhz f in = 10mhz f in = 100khz f in = 500khz f in = 1mhz f in = 3mhz f in = 7mhz f in = 10mhz application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
9 CXD2312R application circuit 2. startup calibration + external sync calibration 2.0v av ss calibration pulse 4.0v 2.0v av dd av ss dv dd dv ss 4.0v av dd av ss av dd av ss dv ss clock input ce oe clk minv linv testmode av dd sel dv ss reset tin to tstr at v in nc cal ts av ss av ss dv dd nc nc dv ss av ss vrb vrb nc nc nc vrt vrt av ss av ss av dd av dd is all 0.1f sample & hold 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av dd digital output d1 d2 d3 d4 dv ss dv dd d5 d6 d7 d8 d0 1 2 3 4 5 6 7 8 9 10 11 12 nc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
10 CXD2312R application circuit 3. only startup calibration (less than supply voltage fluctuation range of av dd = 100mv and reference voltage fluctuation range of |vrt vrb| = 200mv) 2.0v av ss 4.0v 2.0v av dd av ss dv dd dv ss 4.0v av dd av ss av dd av ss dv ss clock input ce oe clk minv linv testmode av dd sel dv ss reset tin to tstr at v in nc cal ts av ss av ss dv dd nc nc dv ss av ss vrb vrb nc nc nc vrt vrt av ss av ss av dd av dd is all 0.1f sample & hold 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av dd digital output d1 d2 d3 d4 dv ss dv dd d5 d6 d7 d8 d0 1 2 3 4 5 6 7 8 9 10 11 12 nc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXD2312R 1. calibration function in order to achieve superior linearity, the CXD2312R has a built-in calibration circuit and a calibration pulse auto generation circuit which is used to execute a calibration circuit. fig. 1 shows a block diagram of the calibration pulse generation circuit. av dd out 14 bit counter 24 bit counter clr clr co co clr sel cal d q 16 1 clk av dd av ss vrt vrb reset ce sence amp 1 sence amp 2 fig. 1. calibration pulse generation circuit (1) startup calibration function over 600 calibration pulses are needed to complete the initial calibration process when the power is first supplied to the ic. the startup calibration function automatically generates these pulses internally and completes the initial calibration process. the following five conditions must be satisfied to initiate the startup calibration function. a) the voltage between av dd and av ss is approximately 2.5v or more. b) the voltage between vrt and vrb is approximately 1v or more. c) the reset pin (pin 15) must is high. d) the ce pin (pin 24) must is low. e) condition b is met after condition a. once all five of these conditions have been met, the calibration pulses are generated. the pulses are generated by counting 16 main clock cycles on a 14-bit counter and closing the gate when the carry-out occurs. therefore, the time required for startup calibration after the above five conditions have been met is determined by the following formula: startup calibration time = main clock cycle 16 16,384 for example, if the main clock frequency is 14.3mhz, the time required for startup calibration is 18ms. when reset = high and ce = low av dd vrt vrb 1v [v] 5 2.5 0 [ t ] sence amp 1 sence amp 2 clr
12 CXD2312R (2) auto calibration pulse generation function after startup calibration is completed, this function periodically generates calibration pulses so that calibration can be performed constantly without any need for input of calibration pulses from an external source. this function counts 16 main clock cycles on a 24-bit counter and uses the carry-out as the calibration pulse. the cycle of the calibration pulse generated in this fashion is as follows: internal calibration pulse generation cycle = main clock cycle 16 16,777,216 therefore, if the main clock frequency is 14.3mhz, the calibration pulse cycle is approximately 19 seconds; since calibration is performed once every seven pulses, the calibration cycle is approximately 130 seconds. in order to use this function, the sel pin (pin 17) must be high. note that this function cannot be used if fixing the lower bits in the calibration operation as described below will cause problems because this function is executed asynchronously without regard to the input signals. (3) external calibration pulse input function if the auto calibration function cannot be used, calibration can be performed in synchronization with the input signals when a calibration pulse is input from the cal pin (pin 41) by setting the sel pin (pin 17) low. 7clock 1clock or more clk cal d4 to d8 d0 to d3 10ns or more n 3 n 2n 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n 3 n 2n 1 n n + 5 fig. 2. calibration timing chart calibration starts when the falling edge of the pulse input to the cal pin (pin 41) is detected. because the lower comparator is occupied for four clock cycles at this point, the previous lower data is held for four clock cycles after seven clock cycles since the rising edge of the clock cycle in which the falling edge of cal was detected. calibration can be performed outside of video intervals by using the sync signal, etc., to input the cal signal. an example of this is shown below. (1) inputting cal every h-sync input clk cal
13 CXD2312R (2) inputting cal every v-sync input clk reset cal it is also possible to use only the startup calibration function by leaving the sel pin (pin 17) low and fixing the cal pin (pin 41) either high or low. note that this method requires restriction of the fluctuation range of the supply voltage and the reference voltage. (4) re-initiating the startup calibration function the startup calibration function can be re-initiated after the power and reference voltage are supplied by using the ce pin (pin 24) and the reset pin (pin 15). particularly in cases where the riseup characteristics of the power supply and the reference voltage are unstable, it is possible to initiate startup calibration properly by connecting a cr and delaying startup until after power supply riseup. reset av dd av ss 15 r c [v] [ t ] reset av dd vrt vrb fig. 3. initiation of the startup calibration function using the reset pin
14 CXD2312R 2. power supply to prevent the influence of noise, connect the power supply to a 0.1f by-pass capacitor as near the device as possible. 3. dv dd either a 3.3v or 5.0v digital power supply can be used. compared to the 5.0v power supply, the 3.3v power supply generates a decreased amount of radiation noise but offers a decreased drive capacity. these two power supplies do not virtually differ in static and dynamic characteristics. further, the high output level rises up to dv dd . 4. reference input the voltage to be supplied to the reference pins must be driven by a buffer having a 10ma or more drive capacity. for supplied voltage stabilization, connect the buffer to a 0.1f by-pass capacitor as near the pins as possible. 5. latch-up ensure that the av dd and dv dd pins share the same power supply on a board to prevent latch-up which may be caused by power on time-lag. 6. board to obtain full-expected performance from this ic, be sure that the mounting board has a large ground pattern for lower impedance. it is recommended that the ic be mounted on a board without using a socket to evaluate its characteristics adequately.
15 CXD2312R 25 23 21 20 0 25 50 75 17 15 13 20 0 25 50 75 av dd = 5.0v dv dd = 3.3v fc = 1mhz cl = 20pf 60 50 40 100k 1m 10m av dd = 5.0v dv dd = 3.3v fc = 20mhz v in = 2vp-p ta = 25 c 9 8 7 100k 1m 10m av dd = 5.0v dv dd = 3.3v fc = 20mhz v in = 2vp-p ta = 25 c 60 50 40 100k 1m 10m av dd = 5.0v dv dd = 3.3v fc = 20mhz v in = 2vp-p ta = 25 c 6 4 2 20 0 25 50 75 av dd = 5.0v dv dd = 3.3v fc = 1mhz 30 25 20 20 0 25 50 75 35 1 1 3 100k 1m 10m av dd = 5.0v dv dd = 3.3v fc = 20mhz v in = 2vp-p ta = 25 c 0 2 tsl tsh supply current vs. ambient temperature fc = 20mhz fin = 1khz triangular wave av dd = 5.0v dv dd = 3.3v output data delay vs ambient temperature input frequency vs. snr input frequency vs. effective bits input frequency vs. sfdr sampling delay vs. ambient temperature maximum operating frequency vs. ambient temperature fin = 1khz triangular wave av dd = 5.0v dv dd = 3.3v input band ambient temperature [ c] ambient temperature [ c] supply current [ma] maximum operating frequency [mhz] ambient temperature [ c] ambient temperature [ c] output data delay [ns] sampling delay [ns] input frequency [hz] input frequency [hz] snr [db] sfdr [db] input frequency [hz] input frequency [hz] effective bits [bit] output level [db] example of representative characteristics
16 CXD2312R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin 42/copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 solder plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : solder (0.18) (0.127) 0.18 ?0.03 + 0.08 0.127 ?0.02 +0.05
17 CXD2312R sony corporation package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 0.02 + 0.05 a 1.5 0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0 ? to 10 ? detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03

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